Di-function multiplexers and multipliers



June 24, 1958 F. s. STEELE DI-FUNCTION MULTIPLEXERS AND MULTIPLIERS 4 Sheets-Sheet 2 Filed Nov. '22, 1952 June 24, 1958 F. e. sTEELE DI-FUNCTION MULTIPLEXERS AND MULTIPLIERS Fil ed Nov. 22, 1952 4 Sheets-Sheet 3 INVENTOR. FLOYD Cr. STEELE June 24, 1958 F. G. STEELE 2,840,306

DI-FUNCTION MULTIPLEXERS AND MULTIPLIERS Filed Ndv. 22, 1952 4 Sheets-Sheet 4 IIIJEQ r k HZ/ 'r 2 is lj +10 +1 +L' +J 2 +52 +12 '2 +13 +53 IN V EN TOR.

FLOYD G. STEELE United States Patent DI-FUNCTIGN MULTIPLEXERS AND MULTIPLIERS Floyd G. Steele, La Jolla, Calif., assignor to Digital Control Systems, Inc., a corporation of California Application November 22, 1952, Serial No. 322,094 16 Claims. (Cl. 235-61) This invention relates to di-function multiplexers and multipliers and, more particularly, to devices for multiplexing a plurality of di-function signals and for multiplying a pair of di-fuuction signals.

Properties of information expressed in di-function signal form are described at length in the co-pending U. S. application for patent, Serial No. 311,609, filed September 26, 1952, for Computer and Indicator System, to Floyd G. Steele. Briefly, (ii-function signal information is in "the form of alternate high and low voltage levels, each of the levels appearing for an integral number of timing intervals. A high or low voltage level appearing for one interval is defined as an instantaneous +1 or -1 di-function value, respectively, and the information contained in such a signal is determined by the relative frequency of occurrence of one value relative to the other. For example, shaft rotation may be converted into a di-function signal, and for no overall shaft displacement, the di-function signal corresponding thereto would comprise alternate +1 and 1 values appearing during successive timing intervals. This value sequence indicates complete lack of shaft rotation by the equal frequency of value o'ccurrence. Then, upon shaft rotation in one direction, an excess or greater number of +1 values compared to 1 values would be generated during the period of such shaft rotation. Conversely, if such shaft rotation should occur in the opposite direction, then an excess of 1 values would be generated in the (ii-function signal corresponding thereto.

The excess of +1 or 1 values over the other, as the case may be, generated during a period of time maybe utilized in determining the actual shaft displacement or the average velocity of shaft rotation during such period of time. Although di-function information is, like shaft rotation, essentially non-numerical in form, this latter use converts such information into a numerical representation as understood and used in the mathematical interpretation of physical phenomena.

Another numerical interpretation of di-function information has resulted in defining the value, as distinguished from an instantaneous value, of a di-function signal as being equal to, for a time period having a given number of timing intervals, the number'of +1 instantaneous values minus the number of 1 instantaneous values occurring during the period of time divided by the number of timing intervals in the period. Thus, from the previous exampleof a non-rotating shaft, the (ii-function signal representing such zero shaft displacement would have a zero value.

In the patent application referred to, shaft rotation was converted into a corresponding di-function signal and, in addition, the arithmetic operation of di function serial half-addition or averaging was performed between two of such signals. Also, an operation of di-functi on deconversion was illustrated in which diunction information was changed into pulse form suitable for counting. The multiplexers and multipliers of the present invention illustrate other fundamental operations of an arithmetic nature capable of being performed between di-function signals.

In particular, one multiplexing embodiment of the present invention multiplexes or interlaces a pair of input di-function signals into a single output di-function signal. This is accomplished by alternately generating in the output signal, the consecutive di-function values of the. two input signals such that each value of each input signal appears for half of its duration in the multiplexed signal. Such multiplexing operations result in the multiplexed signal having one-half the timing scale of the two input signals with its di-function value being equal to, as defined, the di-function full sum of the input signals. Hence. di-function multiplexing is equivalent to di-function full-addition and the result of such an arithmetic process may be contrasted with difunction half-addition or averaging as performed by the half-adder of the previously referred to application.

Half-addition or averaging of two input di-function signals results in a third di-function signal having the same timing scale as the input signals and containing +1 and +1 instantaneous values when the two input signals are concurrently at +1 and +1 values, respectively. During the timing intervals such input signals differ in value, their average may be a +1 value for the first interval of diiference and then will alternate between 1 and +1 values during all remaining timing intervals of value difference. In this way, an effective di-function value of zero is obtained when considered for any two successive intervals of input signal difference, which effective zero value is equal to the average of simultaneously appearing +1 and 1 values. As the result of this type of operation, the output half-adder signal is in error for substantially half of the time owing to the averaging required to obtain an effective zero value.

The full-addition process inherently performed in multiplexing removes the error noted above in half-addition since the multiplexed result of +1 and +1 simultaneously appearing values in the input signals are positioned adjacent each other with respect to time in the multiplexed signal, each value thereof being foreshortened in time by a factor of one-half.

In addition to the two signal multiplexer embodiment, another version thereof is illustrated which is capable of interlacing four input signals so as to obtain the di-function full-addition thereof. The method of deriving this latter multiplexer is set forth to enable the ready design of one capable of interlacing 2 input signals, the four signals multiplexed by the second embodiment being a special case where n=2.

A pair of (ii-function multiplier embodiments are described and illustrated, one of which multiplies each two adjacent di-function values in a multiplexed signal to produce, as defined, a chain product of the original difunction signals forming the multiplexed one. This is accomplished by delaying the multiplexed signal one timing interval and then deriving the direct instantaneous difunction product of each simultaneously appearing pair of values in the multiplexed and delayed multiplexed signals.

In the other multiplier embodiment, two parallel difunction input signals are multiplied, a requirement on the input signals being that the timing scale of one be a multiple of the timing scale of the other. This is necessary to remove inaccuracies, as described in detail later, which would normally result in the parallel multiplication of two di-function signals having the same time basis. The product is obtained between the signals such that each instantaneous value of the shorter scaled signal is multiplied with the concurrently appearing value of the the shorter time basis.

It is, therefore, the principal object of the present invention to provide devices for multiplexing and multiplying di-function signals.

Another object of the present invention is to provide a device for multiplexing a pair of iii-function signals and multiplying each pair of adjacent di-function values in the multiplexed signal. i

Still another object of the present invention is to provide' a device for multiplexing a pair: of di-function signals, delaying the multiplexed signal one timing interval, and multiplying simultaneously appearing multiplexed and delayed multiplexed signal values together.

Another object of the present invention is to provide a device for multiplexing a pair of input di-function signals to form a third di-function signal having one-half the timing basis of the input signals.

Still another object of the present invention is to provide a device for alternately generating in an output difunction signal each consecutive di-function value of a pair of input (ii-function signals.

A further object of the present invention is to provide a device for multiplexing 2 di-function signals to obtain an output di-function signal having 1/2 the time basis of the input signals.

A still further object of the present invention is to provide a device for sequentially generating in an output di-function signal each of the simultaneously appearing di-function values of 2 input'signals whereby the multiplexed output signal represents a di-function full-addition of the input signals.

Another object of the present invention is to provide a device for multiplying each pair of adjacent di-function values in a multiplexed di-function signal.

Stillanother object of the present invention is to provide a device for delaying a multiplexed input signal one timing interval and consecutively. multiplying each pair of simultaneously appearing values in the multiplexed and delayed multiplexed signals to form 'a di-function cross-product of the two di-function signals originally multiplexed to form the multiplexed signal.

A further object of the present invention is to provide a device forconsecutively multiplying simultaneously appearing values in a pair of di-function signals.

A still further object of the present invention is to provide a device formultiplying a pair of input di-function signals having different timebases.

A further object of the present invention is to provide 7 a device for multiplying each, di-function value ofone di-function signal having one time basis with alldifunction values, appearing during its occurrence, of another di-function signal having a shorter time basis.

Other objects and features of the present invention will be readily apparent to those skilled in the art from the following specification and appended drawings wherein is illustrated a preferred form of the invention, and in which: a

Fig. 1 is a block schematic diagram of a di-function multiplexer and multiplier system according to the present invention; l i a Fig. 2 is a detailed circuit diagram of the di-function multiplexer according to Fig. 1-; i

Fig. 3 is a detailed circuit diagram of the di-function multiplier according to Fig. 1;

Fig. 4 is a composite group of signal waveforms illustrating the principles of operation of the system according to Fig. 1; i

Fig. 5 is a circuitdiagram of another form of difunction multiplier according to the present invention;

Fig. 6 is a composite group of signal Waveforms illustrating the operation of the multiplier according to Fig. 5; c Fig; 7 isa circuit diagram of another form of di-function multiplexer according to the present invention; and

Fig. .8 is a composite group of signal waveforms illustlrqating the operation of the multiplexer according to ig. 7;' i

Referring now to the drawings, wherein like elements are given the same numerical designation, trated in Figure 1, one form of a di-function multiplexer and a di-function multiplier according to the present invention. The multiplexer 10 receives a first pair of complementary input di-function signals a and a, respectively, produced on the two output conductors of an electronic switching device, such as flip-flop A, and a second pair of complementary input di-function signals b and 11', produced on the two output conductors of another electronic switching device, such as flip-flop B. Flip-flops A and B maybe, by way of example, the principal fliptlops of a pair of di-function quantizers of the type illustrated and described in the before referred to application for patent.

Briefly each of these quantizers serves to convert the rotation of a shaft into a corresponding di-function signal. This is done by sensing the motion of the shaft by having an energized segment thereon make sequential contact with three brushes whose signals feed a diode gating network serving, in turn, to trigger three flip-flops, one being termed the principal one. This principal flipflop is normally triggered by the gating network and the other flip-flop conduction states to produce a zero valued output signal, but responds to each predetermined amount of shaft rotation in one defined direction, as sensed by the brushes, to produce an extra +1 output value and responds to the same amount of shaft rotation in the other direction to produce a single extra l value. Such a quantizer is clocked, and as will be apparent later, signal cl from source 11 will be of the proper phase and frequency to provide this timing function.

A timing signal source 11 produces a first square wave output timing signal cl comprising a series of alternate high and low voltage levels, signal cl being applied as an input signal to both multiplexer 10 and frequency divider 12. Signal source 11 may be a conventional multi-vibrator circuit, a blocking oscillator circuit, etc. and the duration of each adjacent low and high voltage level of signal cl marks, as is hereafter referred to, a signal cl timing interval. Divider 12 produces a pair of complementary output timing signals, c and c which, in turn, are applied to two input terminals of multiplexerv 10. The duration of each adjacent low and high voltage level of signal 0 marks or indicates, as is afterwards referred to, a signal 0 timing interval. Frequency divider 12 and multiplexer 10 are illustrated and described in detail in connection with Figure 2 of the present disclosure.

The pair of complementary output multiplexed signals d and d produced by multiplexer 10 are applied to two of the input terminals of a di-function multiplier 13, signal cl being applied to a final input terminal thereof. Multiplier 13, to be illustrated and described in detail in connection with Figure 3 of the present disclosure, produces a pair of complementary output di-function signals f and f on its two output conductors, respectively.

Frequency divider 12 converts signal cl into a similar signal c having one-half the frequency thereof, signal 0 providing the time basis of di-function signals a, a, b and b, each instantaneous value thereof appearing for one signals timing interval. Thus, two consecutive signal cl timing intervals are produced during appearance of each instantaneous di-function value of the above signals.

Multiplexer 10 acts to multiplex or interlace signals a and b such that its output signal d comprises a difunction signal having each of the instantaneous di-function values of a and b but reduced one-half in time scale. This is accomplished by triggering flip-flop D at the end of the first half of any given signal c timing interval to produce in signal d, the di-function value of signal a during the given interval and then triggering flip-flop D at the end of the given interval to produce in signal cl there is illustial.

during the first half of the next timing interval the difunction value of signal b for the given timing interval. Stated differently, if each signal c interval is considered as occurring during first and second consecutive signal cl intervals, then the value of signal a is generated in signal (1 during the second signal cl interval, the value of signal 5 being generated in signal (I during the first cl timing interval of the next signal c interval. The timing scale of signal if is consequently determined by signal cl and each di-function value thereof lags by one cl interval the appearance of its corresponding value in signal a or b.

Multiplier 13 multiplies each di-functional value of signal (1 and the succeeding value and the result of such multiplications, measured by timing signal cl, appears as consecutive instantaneous di-function values in the multipliers output signal f. The result of such a multiplication is here defined as a chain or cross-product.

Referring now to Figure 2, there is illustrated in detail multiplexer 1t) and frequency divider 12.

For the purpose of clarity, each bi-stable flip-flop is schematically illustrated by a box having its alphabetical designation placed therein in capitalized form. in addition, the two output conductors are each designated by the fiip-fiops letter, lower case, with one being primed to indicate the complementary signal. The two input conductors are designated by S, signifying set, and Z, signifying zero, each being followed by the lower case alphabetical connotation given its flip-flop. Electronically, the input and output designations mean that a triggering signal applied to the S or set conductor triggers the flip-flop such that the signal appearing on the unprimed output signal conductor goes to the high voltage level, taken here to represent the binary one value, with, as a necessary consequence, the signal appearing on the primed signal conductor taking the reverse cr low voltage level. On the other hand, a triggering signal applied to the Z or zero conductor causes the reverse conduction state from that described above to be produced with the unprimed output signal going low, representing the binary value of zero, and the primed signal taking the high level.

Considering the representation employed for the gating network, those boxes having the cross-mark, X, therein are logical and gating circuits and may, quite obviously, take various forms as understood in the art. Onepreferred type is the crystal diode type wherein each input signal is applied to the cathode of an associated crystal diode, preferably of the germanium variety, the anodes of the diodes therein being jointly coupled througha high valued resistor to a source of high positive potential. The junction formed between the'diode anodes and resistor end then forms the output terminal of the circult and will be at the high voltage level only upon all input signals to the circuit being simultaneously high and will be at the low level upon any combination or all of the input signals being likewise at the low level.

The logical or gating circuits are represented by blocks having a plus mark, therein and are preferably similar to the and gates described above except that the diode directions are reversed and the resistor therein is connected to a source of high negative poten- In such circuits, the junction between the diode cathodes and resistor will be at the high voltage level whenever any or all of the input signals are high and V will be low upon all of such input signals being simultaneously at their low voltage levels.

As will be understood, innumerable variations exist in bi-stable flip-flop designs suitable for use with the above described preferred types of'iogical gating circuits. Accordingly, the choice of a proper flip-flop capable of being triggered by such'gatin'g circuits may be readily ,made' by one skilled in the art.

In any event, the flip-flop and gating circuit symbols found herein andin the remaining figures. are identical to those used in the before referred to application for patent and the structure signified thereby may be likewise identical.

In Figure 2, signal cl is applied within divider 12 to one input terminal of each of a pair of two terminal and gating circuits 15 and 16, the output terminals of which are connected to the S and Z input conductors, respectively, of an electronic switch, such as flip-flop C. The output signal 0 of flip-flop C is applied to the other input terminal of gating circuit 16, While the complementary output signal 0' of flip-flop C is applied to the other input terminal of gating circuit 15.

in operation, if signal 0 is at its high voltage level, then circuit 16 will have a high voltage level applied to its input terminal corresponding thereto and timing signal cl, upon rising to its high voltage level during the last half of its timing interval, will prepare flip-flop C for firing through its Z conductor. Then, upon signal cl switching to its low voltage level at the end of the timing interval, flip-flop C will accordingly be triggered with signals 0 and 0 switching to the low and high levels, respectively. Then, at the end of the next signal cl tim ing interval, flip-flop C will be triggered similarly through its 3,, input conductor, owing to the action of gating circuit 15, with signals 0 and c returning to their high and low voltage levels, respectively. In considering signal 0, it is seen that it assumes consecutive low and high voltage levels during two successive signal cl timing intervals and hence constitutes the desired frequency division thereof.

in considering the derivation of multiplexer 10, reference is made to Programming Table 1 included next:

Programming Table 1 Lines a b c d Sal Zn All possible combinations of signal a, b and c difunction values are found in columns 1, 2 and 3 and on linesl through 8 of Table 1. Square wave timing signal 0 may be included by considering its alternate high and low voltage levels as constituting a zero valued di-function signal having consecutive +1 and 1 instantaneous values, respectively, each of which appears for one signal cl timing interval. Thus, on lines 1 and 2 of Table 1, for example, with signals a and b both equal to +1,

signal 0 may have a +1 value as indicated on line 1 or a 1 value as indicated on line 2.

As stated previously, input signals are to be applied to flip-flop D at the end of each signal cl timing interval so as to alternately produce in signal d, the respective values of signals a and b. This is provided for in Programming Table 1, as may be readily seen from lines. 3 and 4, where signals a and b have the values of +1 and -1, respectively. Thus, on line 3 Where signalqc equals 1 for the rst half of its signal cl timing interval, signal d in column 4 is to be set equal to +1, the value of signal a, at the end of this first half interval. 011 line'4, during the second half of the same timing interval where c equals to +1, signal :1 is to be set equal to -l, the value of signal b, at the end thereof. Signal d is set equal to +1 for the programming defined on line 3 by applying a triggering signal to the S input conductor of flip-flop D as indicated in c'olumn'S. in the same way,

as indicated on line 4, column 6, signal a is set equal to ductor of flip-flop D as indicated in colurnn 6.

I logical tautalogies, to:

In the same manner, the unreduced equation for the Z input conductor gating circuitry may be written from Table 1 as:

From Equations 2 and 4 may be drawn the gating circuitry connected to the S and Z conductors, respectively, as specifically illustrated in Figure 2. A detailed description of the manner ofmechanizing Boolean equations into circuitry although known to those skilled in the art may be found in the before referred to application for patent. As will be appreciated, the individual and and or gating circuits, here'indicated as blocks, may be similar to the detailed circuitry corresponding thereto as set forth in Figure 3 of the referred to patent application. As is well known, manipulations of Boolean equations, such as Equations 2 and 4, by logical mathematical rules, yield other equations and hence other gatingnetworks capable of producing the same results as the specified circuitry herein illustrated. Obviously, no invention would be involved in such manipulations of these equations nor in other specific equations to be derived later in connection with other forms of the present invention.

The process of multiplexing two di-functi'on signals, re sults in the multiplexed signal being equivalent to, as defined,.the di-function full sum of the two input signals; In

other words, multiplexing a pair of signals produces the di-function full-addition thereof as measured by the difunction values of the multiplexed signal at its reduced time scale. Di-function full-addition then, is an arithmetic process in which each pair of simultaneouslyappearing (ii-function values of the two input signals appear consecutively with'respect to time in the output multiplexed signal.

- The process ofdi-function averaging or half-addition, on the other hand, as explainedin thereferred to application, produces a signal having the same time scale as the two input signals, but whenever the actual instantaneous sum of zero is required, as when the two input signals differ in value, a +1 output value, for example, may be produced, which value is remembered by the conduction state of a memory flip-flop, so that during the next interval the input signals differ in value, a 1 value is produced. This 1 value averages with the before mentioned +1 value to form the required Zero value. Thus, the values of +1 and +1 are consecutively produced during consecutive timing intervals that such input signal values differ. The result of half-addition is consequently in error in the above example from the time the stated +1 value was produced until the 1 value appeared. This deficiency of di funetion halt-addition is eliminated in the full-addition herein exemplified since the zero result is realizedby consecutively appearing+l and '1 values in the multiplexed signal.

If a first di-function'signal were multiplexed with the complement. of a second .dl-fUflCtlQn signal, the value of the resulting multiplexed signal would be equivalent to the full-subtraction of the second from the first of such signals. This follows directly from the fact that the difunction value of the first signal would be added to the inverted or negative value of the second signal, the result thereof being subtraction.

Referring now to Figure 3, there is illustrated a detailed circuit diagram of di-function multiplier 13 according to the present invention. As stated previously, multiplier 13 multiplies each instantaneous di-function value and the succeeding value of signal d and produces an output instantaneous (ii-function value corresponding to the result thereof in its output signal f.

This is accomplished by delaying through a flip-flop E each til-function value of signal d one signal cl timing interval, and then comparing all concurrently appearing values of signal d and signal e, the output signal of flipfiop E, and producing the instantaneous di-function products thereof. By definition, the di-function product of a pair of +1 or 1 values is equal to +1, the product of a pair of different values being equal to l. Thus, if two adjacent di-function values are different in value, their product is 1, while if similar in value, their product is +1.

Flip-flop E' is triggered to provide the required time delay of signal (I by applying signals d and d to one input terminal of each of two two-terminal and gating circuits, the output terminals of which are connected to the S and Z input conductors, respectively, of flip-flop E. Timing signal cl is then applied to the other input terminal of each gating circuit with the result that at the conclusion of each timing interval signal d is high, flipfiop E is actuated through its S input conductor to produce a high voltage level in signal e and is further actuated through its Z input conductor at the conclusion of each timing interval. Signal d is high to produce a low voltage level in signal e. Accordingly, each signal d value is transferred to signal e at the conclusion of its respective timing interval.

The derivation of the remaining circuitry of Figure 3 may be most readily understood from Programming Table 2 included next:

Programming Table 2 Lines d e f S! Zr In columns 1 and 2 of Table 2 are found the four possible di-function value combinations of signals d and e while, in column 3, is found the resultant di-function product thereof to be generated in signal f. Thus, on lines 1 and 4 where signals a and e have identical values, signal 1 is to be set equal to +1, while on lines 2 and 3 where signals d and e differ in value, signal f is to be set equal to -l. In columns 4 and 5 are found the required triggering signals to be applied to the S and Z; input conductors for programming the signal f values indicated in column 3. As will be apparent, each signal 1 value will be the product of the signal a and e values appearing during the preceding timing interval since each flip-flop F triggering operation is performed at the end of a timing interval.

From columns 4 and 5, and including remembering timing signal cl, the Boolean equations defining the gating circuitry to be connected to the S; and Z; input conductors may be written as:

(Eq. 5) q- The multiplier circuit of Figure 3 is a mechanization 9 of Equations 5 and 6, including the triggering circuitry previously described for delay flip-flop E.

The operation of multiplier 13 and multiplexer 10 of Figure 1 may be best understood by reference to the composite group of signal waveforms illustrated in Figure 4. First illustrated is timing signal cl appearing during a series of designated signal cl timing intervals. Timing signal c is also illustrated-signal cappearing during a series of designated signalcc timing intervals. Signal complementary to signal a, is'also illustrated in Figure 4, as are input di-function signals a and b, given by way of example. The consecutive instantaneous values of signal a during the 1st, 2nd, 3rd, etc., signal 0 timing intervals are designated a a 11 etc., while the corresponding values of signal b during the same timing interval are designated b b b etc.

During the 1st signal 0 timing interval, signals a and b are at their high and low voltage levels, or a and b values, respectively, the result being that flip-flop D is triggered at the end of the 1st signal cl timing interval to produce in signal d the high or al value of signal a during the 2nd signal cl timing interval, and is then triggered at the end of the second cl timing interval to produce in signal d, during the 3rd cl timing interval the low voltage or b value of signal b.

During the 2nd signal 0 timing interval, signals a and b are still at high and low, or a and b values, respectively, with signal d being correspondingly at high and low voltage levels during the 4th and 5th cl timing intervals, respectively. During the 3rd signal 0 timing interval, signals a and b are simultaneously at their low voltage level, or :1 and b values, respectively, with signal at being at the low voltage level during both the 6th and 7th signal cl intervals. In like manner, signal d, during the remaining timing intervals, as illustrated, may be readily understood.

Signal e of flip-flop E is next illustrated, signal e being similar to signal at but delayed by one signal cl interval with respect thereto, signal e having, during the 2nd designated cl timing interval, the value b or low level, not before illustrated, of signal b.

Signal 1, next illustrated, is the, as defined, chain product of the di-function values of signals d and e, signal 1, in practice, being delayed one timing interval to the right as viewed from Fig. 4. Consequently, dur-' ing the 2nd cl timing interval, signals d and e being at their a and b or +1 and +1 di-function values, respectively, signal 1 has a -1 value appearing during the 3rd cl timing interval, which value, designated a b is the di-function product thereof. During the 3rd cl timing interval, the b and a or,1 and +1 values of signals d and e, respectively, result in the product a b of signal 1 being equal to l as it appears during the 4th timing interval. In the same manner, the remaining product values of signal may be readily ascertained and understood. 7

The multiplication function performed by chain multiplier 13 may be mathematically expressed by considering signal a as comprsing the series of di-function values in the equation a +a +a +a and considering signal b as comprising the series of di-function values in the equation b +b +b,,, wherein identically numbered subscripts of the two equations occur simultaneously with time. In the above and following equations, each of the series of indicated difunction values will represent either an actual +1 or 1 value. The equation of multiplexed signal a may be expressed by the equation while chain product signal may be expressed by the equation 7 As will be observed from the resulting equation, each instantaneous value of signal a is multiplied both by the instantaneous value of signal b occurring simultaneously in time therewith and the value of signal b occurring during the preceding timing interval. Hence, every other value of signal 1 is a cross-product of the two input signals.

Referring now to Figure 5, there is illustrated another di-function multiplier 20, producing, as defined, direct di-iunction' multiplication, according to the present invention. l'ylultiplier 2i differs from multiplier 13 in that it directly multiplies the simultaneously appearing di-function values of two paralleled input di-function signals instead of cross-multiplying the values of a multiplexed signal in the manner of multiplier 13. However, a definite relationship between the di-function signals multiplied by multiplier 2% is required, the relationship being that the timing base of one signal be a multiple of the other.

This relationship is required, since, if the input signals had the same time base and were substantially zero fact, the accuracy of the direct 'cuitry connected between the signal g, g, h, h

valued, then the output signal obtained from such direct multiplication might be either a substantially continuous +1 value or a substantially continuous 1 value, depending on the relative phasing between the alternate +1 and l values in the two input signals. For example, if one signal, at a given time interval, had a +1 value and then consecutive l and +1 values thereafter, while the other signal contained a 1 value at the given time interval, and consecutive +1 and -1 values thereafter, the direct product of the two signals would be a continuous series of 1 values. On the other hand, if each signal had a 1 value at the given time interval with consecutive +1 and 1 values thereafter, their product would comprise a series of consecutive +1 values. The products in both examples would be erroneous since the direct product of two substantially zero valued di-function signals should be substantially equal to zero.

' However, by multiplying two di-function signals having different time bases wherein the duration of timing intervals marking one is a multiple of the duration of timing intervals marking the other, the above-noted error owing to phase differences is substantially reduced. In

product will be dependent on the ratio between the two timing interval durations, the phase displacement error decreasing as the diiference between timing interval durations becomes greater.

In Figure 5 are shown two electronic switches, such as flip-flops G and H, producing pairs of complementary output di-function signals 3, g and h, h, respectively, said signals being applied as input signals to direct multiplier Ztl. These flip-flops may again be the principal ones within a pair of quantizers, as before described in conjunction with flip-flops A and B of Figure 1, but

clocked by dilierent timing signal frequencies as here- Y inafter described. Since, as has been mathematically definedQidentical (ii-function values yield an instantaneous product of +1 and different di-function values yield an instantaneous product of l, the gating circon- ductors and the S and Z input conductors of the product ilip-fi'op I within multiplier 28 is identical to the gating circuitryconnected between the signal d, d, e and e conductors and the S and Z input conductors of flipflop in Figure 3. This circuit similarity exists even though'one di-function signal in this case has a longer time basis than the other signal since the longer time basis signal may be considered as always having more V than one consecutive +1 or 1 instantaneous value as marked by the shorter time intervals. Another restriction on the multiplier 20 is that the input timing signal applied thereto should be the one marking or measurtiming scale of signal g,'it is apparent that between the .two would be equally operable. In some -Timing source 11 is 1 being divided by a timing intervals each instance signal is marking ing the di-functio'n input signal having the shorter time basis.

i In Figure 6 is found a composite group of signal wave-forms illustrating the principles of' operation of multiplier 20, wherein signal g, having the shorter time basis is illustrated, as is signal cl marking the values thereof. The successive values of signal 'g during the designated timing intervals of signal cl are'denoted by g g g etc. Signal 11 is illustrated, and for the purpose of this illustration, has a timing scale five times that of signal g. Hence, the successive values of signal h are denoted by h h h etc., each value appearing for five signal cl timing intervals.

The product of signals g and 11 appear in the output signal i produced by an output flip-flop I and each value thereof, marked by signal cl, is the product of the instantaneous difunction values of signals g and h but delayed one cl timing interval with respect thereto. Thus, the consecutive values of signal i appearing during the 2nd, 3rd, 4th, etc. timing intervals of signal cl are designated by g I1 g,; h;, g;, h, etc., respectively. As will be apparent from inspection of the wave-forms of Figure 6, different values of signals g and h result in a --1 signal i value while identical values, whether +1 or -1, result in a +1 signal 1' value. Although signal It has been illustrated as having five times the other ratios instances, the ratio may be on the order of 100 to 1, in which case, a highdegree of accuracy in the product signal would be obtained. 7

Referring next to Figure 7, there is illustrated a four signal multiplexer 22 according to the present invention. again illustrated, its output signal cl first frequency divider 24 similar to divider 12 of Figure 2, into a pair of complementary output signals 11 and n which, in turn, are divided by a second frequency divider 26 into a pair of complementary output signals 0 and 0'. Timing signals cl, n, n', o and 0 are applied to multiplexer'22 as are the four pairs of complementary signals to be multiplexed, designated and j, k and k, l and l, and m i and m, produced by flip-flops I, K, L and M, respectively.

These latter flip-flops may again comprise the principal flip-flops within four separate di-function quantizers, all-clocked "relative to signal 0, as will be more specifically brought forth later.

The frequency dividing operation on signals 11 and n of divider 24 performed by divider 26 is identical to that performedby divider 24 on signal cl, the result being that signal 0 is one-fourth and one-half the frequency of signals cl and n, respectively. As is also apparent, the two frequency dividers constitute a conventional scale-of-two counter, wherein complementary output counting signals are available at each stage. The timing intervals measured by each successive low and Programming Table 3 7 Input Signals Timing Output Signals Line j k I m n o S, Z,

-1 -1 1 1 l l 1 1 1 1 1 1 1 l l 1 1 1 1 l 1 1 1 1 On lines 1 and 2, '3 and 4, 5 and 6, 7 and 8, of Table 3 are found the pairs of possible values of signals 1', k, l and m, respectively, While in columns 5 and 6 are found the four possible combinations of values of signals n and 0, each combination being positioned adjacent a corresponding pair of the input signal values. Since, during each signal 0' timing interval, the values of the four input signals are to be consecutively produced in signal p, it is apparent that these four sets of value combinations of signals n and 0 are required to provide proper program Thus, at the conclusion of the period that n and 0 are simultaneously equal to -1, as on lines 1 and 2, signal 2 is to be set equal to signal j, while when n and 0 are equal to +1 and -1, respectively, as on lines 3 and 4, signal p is to be set equal to signal k, etc. The flip-flop P triggering signals corresponding to the indicated programming are found in columns 7 and 8 and, using timing signal cl, the Boolean equations corresponding to the gating circuitry for performing such programming high voltage levels of signal 0 serve to mark the instantaneous di-functlon values of signals 1, k, l and m, in the manner that signal c marked signal a and b values in the .multiplexer of Figure 2.

In operation, signal cl indicates or marks four of its one instantaneous value in the various input signals. At the end of the first signal cl interval in each signal 0 timing interval, the multiplexer output flip-flop P is triggered to produce during the second cl interval, thecorresponding value of signal 1 inits output signal p. Flipflop P is successively triggered at the end of the secon d,

third, and fourth cl intervals in eachsignal o interval r to produce in its signal p, the values of signals k, l and m, .respectively, signal p thereby having one-fourth, the timing scale of each input signal. f The manner of accomplishing this function, including the derivation of the circuitry therefor, may be most readily understood by referring to the nextincluded Programming Table '3.

I the latter group being by way of example only. During the 1st designated cl timing interval, signals n and 0 are both equal to 1, the result being that output signal p has, during the 2nd cl interval, the value of signal that is a +1 value as indicated by j This one interval displacement arises, as formerly, from the necessity of performing each flip-fiop triggering operation at the conclusion of a timing interval.

During the 2nd cl interval, signals 21 and 0 are equal to +1 and 1, respectively, hence, a signal 2 value of +1, designated k is generated during the 3rd cl interval, valuek being the value of signal k during the first signal 0 timing interval. During the 4th cl timing interval, corresponding to the +1 and +1 values of signals n and i 0, respectively, during the 3rd interval, a +1 value is generated-in signal 2 which +1 value corresponds to the 1 or +1 value of signal I during the lst signalo timing interval. --During the 5th cl timing interval, corresponding to the simultaneous +1 values of signals 12 and 0 during the 4th interval, a, signal p value of +1 is generated corresponding to the +1 or m value of signal m during the 4th interval. During the next four cl timing inter- 'vals, the above described operation is repeated with signal p again successively assuming the 2nd signal 0 timing 7 interval values of signals 1', k, l andm.

The value of multiplexed signal p is the full-sum of input signals 1', k, l and m as defined for signal d in the multiplexer ,embodimentof'Figure 2. Multiplexer 22 is intended to illustrate the principles involved in multiplexing and hence, producingfthe serial or full-addition of 2 input signals, where n is an interger greater than one. As will be observed, the multiplier illustrated in Figure 2 1s a special case of multiplier 22 wherein 'n equals one.

p The principles herein outlined briefly include the provision of n frequency dividers, or a n-stage counter, each pable of producing the desired electrical results.

Although multiplexer 22 has been described as per- 1 forming di-function full-addition, it is apparent that one or more of the input signals may be subtracted, by interchanging their respective pairs of input conductors, from the sum of the remaining ones. If this is done, then as pointed out in connection with multiplexer 10, the inverse or complementary values of the signals to be subtracted are added to the remaining signals, the result being that the value of the di-function output signal will be equal to the sum of the signals to be added minus the sum of the signals to be subtracted.

As Will be apparent to those skilled in the art, other types of switching devices such as relays, etc., may be substituted for the flip-flop circuits utilized in the various multiplexer and multiplier devices illustrated without departing from the spirit and scope of the present invention.

I claim:

1. In combination: means for producing first and second di-function signals; means for multiplexing said first and second di-function signals; and means responsive to the multiplexed first and second signals for producing a signal representing the chain product thereof.

2. A device for use with a pair of di-function signal generators, said device comprising: means for alternately producing in a single di-function signal each di-function value of the pair of signals produced by the pair of generators; and means responsive to each (Ii-function value in said single signal and the succeeding value to produce an output signal representing the di-functional product,

thereof.

3. In combination: means for producing first and second di-function signals; and means for producing in an output signal the instantaneous di-function products of all simultaneously appearing instantaneous di-function values in said first and second di-function signals.

4. The combination of claim 3 wherein said first difunction signal has a predetermined timing interval, and said second di-function signal has a timing interval which is an integral multiple of said predetermined timing interval of said first di-function signal.v

5. A device for multiplexing and multiplying lstand 2nd di-function signals, each of said signals comprising a series of high and low voltage levels, each of said voltage levels appearing for an integral number of timing intervals, said device comprising; first and second electronic switching means, each of the switching means being responsive to 1st and 2nd input signals for producing high and low output voltage levels, respectively; means responsiveto the high or low voltage level appearing in the 1st di-function signal during each timing interval for applying a 1st or 2nd signal, respectively, to said first switching means intermediate the timing interval; means responsive to the high or low voltage level appearing in the 2nd di-function signal during each timing interval for applying a 1st or 2nd signal, respectively, to said first switching means at the end of the timing interval; means for delaying each output voltage level produced by said first switching means one-half of a timing interval; means responsive to identical voltage levels appearing simultaneously in the output voltage level and the delayed output voltage level of said first switching means for applying a 1st signal to said second switching means;

arate pairs of complementary di-function signals a,

14 means responsive to diiferent voltage levels appearing simultaneously in the output voltage level and the delayed output voltage level of said first switching means for applying a 2nd signal to said second switching means whereby the output voltage levels of said second switching means comprise the di-function chain product of the 1st and 2nd di-function signals. a

6. A device for multiplexing first and second di-function signals, each of said signals comprising alternate high and low voltage levels, each of said voltage levels appearing for an integral number of timing intervals, said device comprising: electronic switching means responsive to first and second input signals for producing high and low voltage levels, respectively; gating means responsive to the high or low voltage level appearing during the first half of each timing interval in the first di-function signal for applying a first or second signal, respectively, to said electronic switching means; and gating means responsive to the high or low voltage level appearing during the last half of each timing interval in the second di-function signal for applying a first or second input signal, respectively, to said electronic switching means whereby the voltage levels produced by said switching means contain the voltage levels appearing in the first and second difunction signals in multiplexed form.

7. A device for multiplying a pair of di-function signals, the instantaneous di-function values of the pair of signals appearing alternately for one timing interval each in a multiplexed signal, said device comprising: means for delaying said multiplexed signal one timing interval; and means for producing a di-function signal having the instantaneous (ii-function products of all simultaneously appearing instantaneous di-function values in the multiplexed and delayed multiplexed signals.

8. A device for producing a di-function chain product of a pair of di-function signals, the instantaneous difunction values of the pair of signals appearing alternately for one timing interval each in a multiplexed signal, said device comprising: means for delaying the multiplexed signal one timing interval; actuable means responsive to first and second input signals for producing an output signal representing +1 and 1 di-function values, respec tively; means responsive to simultaneously appearing identical di-function values in the multiplexed and delayed multiplexed signals for applying a first signal to said actuable means; and means responsive to simultaneously appearing different di-function values in the multiplexed and delayed multiplexed signals for applying a second signal to said actuable means.

9. A device for multiplying first and second di-functi-on signals, said device comprising: actuable means responsive to first and second input signals for producing an output signal representing. first and second di-function values, respectively; means for consecutively comparing each difunction value of the first signal with the simultaneous and preceding diunction values of the second signal; and means responsive to eachcomparison performed by the last-named means for applying first and second signals to said actuable means when the compared di-function values are identical and different, respectively.

10. A device for multiplexing first and second sepb and b, each of said signals a and b comprising alternate high and low voltage levels, each of said levels appearing for an integral number of first timing intervals marked by alternately appearing low and high, and high and low voltage levels of complementary timing signals c and 0', respectively, each of the voltage levels of signal 0 and c appearing during alternate low and high voltage levels of a second timing signal cl, said device compris ing: actuable means having first and second input conductors and responsive to input signals applied to said first and second input conductors for producing high and low output voltage levels, respectively; means responsive ternately in a multiplexed signal nated e and e, respectively; 1 and second input terminals and responsive to input signals to high voltage levels appearing simultaneouslyin the a, c' and cl or the b, c and cl signals for applying an input signal tosaid first input conductor: and, means responsive to ahigh voltage level appearing simultaneously in the b, plying an input signal to said second input conductor.

11. A device for multiplexing first andssecond separate pairs of complementary di-function signals a, a, b and b, each of signals a and b comprising alternate high and low voltage levels, each of said levels appearing for an integral number of first timing intervals marked by alternately appearing low and high, and high and low voltage levels of complementary timing signals c and respectively, each of the voltage levels of signals 6 and c appearing during alternate low and high voltage levels of a second timing signal cl, said device comprising: actuable means having first and second input conductors and responsive to input signals applied to said first and second input conductors for producing high and low output voltage levels, respectively; a first gating circuit comprising the mechanization of a function of the Boolean equation (a.c'+b.c).cl for applying input signals to said first input conductor; and a second gating network comprising the mechanization of a function of the Boolean equation ,(b'.c+a'.c).cl for applying input signals to said second input conductor.

12. A device for multiplying a pair of di-function signals, the di-function values and the complementary difunction values represented by said signals appearing ald and a complementary multiplexed signal d, respectively, each of said di-function values appearing for one timing interval marked by adjacent low and high voltage levels in a timingsignal cl, said device comprising: means for delaying signals d and d one timing interval, said delayed signals being designated e and e, respectively; actuable means having first and second input terminals and responsive to input signals applied to said first and second input terminals for producing high and low output voltage levels, respectively; first means responsive to each simultaneous appearance of the high voltage level in signal'cl and the +1 difunction values in signals d and e or d. and e for applying an input signal to said first input terminal; and second means responsive to each simultaneous appearance of the high voltage level in signal cl and the +1 di-function values in signals d and'e or d and e for applying an input signal to said second input terminal.

13. A device for multiplyinga pair of di-function signals, the di-function values and the complementary difunction values represented by said signals appearing alternately in a multiplexed signal d and a complementary multiplexed signal d','respe'ctively,' each of said di-function values appearing for one timing interval marked by adjacent low and high voltage levels in a timing signal cl, said device comprising: means tor'delayingsignals' d and d one timing interval, said delayed signals being desigactuable means having first applied to said first and second input terminals for producing high and low output voltage levels, respectively; a first gating network comprising the mechanization of ,a function of the Boolean equation (d.e+d'.e').cl for applying input signals to said first input terminal; and a second gating network comprising the mechanization of a function of the Boolean equation (d.e'+d.e).cl for applying input signals to said second input terminal.

0 and cl or the a, c and cl signals for ap- 1 14. A device for multiplying first and second separate pairs of complementary di-function signals g, g and h, h, each of signals g and h comprising alternate high and low voltage levels appearing for an integral number of timing intervals, each of said timing intervals being marked by an adjacent low and high voltage level of a timing signal cl, said device comprising: switching means having first and second input terminals and responsive to signals applied to said first and second terminals for producing high and low output voltage levels; first means responsive to high voltage levels appearing simultaneously in the g, h and cl or the g, h and cl signals for applying a signal to said first terminal; and second means responsive to high voltage levels appearing simultaneously in the g, h and cl or the g, h and cl signals for applying a signal to said second terminal.

15. A device for multiplying first and second separate pairs of complementary di-function signals g, g and h, h, each of signals g and h comprising alternate high and low voltage levels appearing for an integral number of timing intervals, each of said timing intervals being marked by an adjacent low and high voltage level of a timing signal cl, said device comprising: switching means having first and second input terminals and responsive to signals applied to said first and second terminals for producing high and low output voltage levels; first gating means comprising the mechanization of a function of the Boolean equation (g.h+g.h).cl for applying signals to said first terminal; and a second gating means comprising the mechanization of a function of the Boolean equation (g.h'+g'.h).cl for applying signals to said second terminal.

16. A device for multiplying a pair of di-function signals, said device comprising: a first di-function generator for producing a first di-function signal having a predetermined timing interval; a second di-function generator for'producing a second (ii-function signal having a timing interval which is an integral multiple of the predetermined timing interval of said first di-function signal; first means responsive to said first andv second di-function signals for producing during each predetermined timing interval of said first di-function signal, a first output signal when said first and second di-function signals are at the same level and a second output signal when said first and second di-function signals are at a difierent level.

References Cited in the file of this patent UNITED STATES PATENTS OTHER REFERENCES Auerbach et 'al.: The Binac, Proc. IRE, January 1952, page 19 relied on.

Progress Report (2) on the EDVAC, MooreSchool, Univ. of Pa. Declassified Feb. 13, 1947 (pages 1-2-13 to 1-2-17; dwg. sht. PYO-107). 

